1. Field of the Invention
The invention relates in general to the fabrication of mixed mode devices, and more particularly to a method of simultaneously forming a gate on a gate oxide layer and forming a capacitor on a field oxide layer.
2. Description of the Related Art
A conventional fabrication process of mixed mode devices comprises forming a pad oxide layer and a silicon nitride layer on a provided substrate. Active regions for forming transistors are defined on the substrate. A part of the silicon nitride layer and a part of the pad oxide layer are removed to form a field oxide layer to isolate the active regions from each other. A first polysilicon layer is formed on the active regions and the field oxide layer. A part of the first polysilicon layer is removed to form a lower electrode positioned over the field oxide layer using a photoresist layer. The silicon nitride layer and the pad oxide layer positioned of the active regions are removed. A gate oxide layer is formed on the active regions by thermal oxidation. At the same time, an oxide layer is formed on the profile of the lower electrode. A conformal second polysilicon layer is formed on the substrate. A silicide layer is formed on the second polysilicon layer. A part of the silicide layer and a part of the second polysilicon layer are removed to form a gate of a transistor and an upper electrode. The gate is formed on the gate oxide layer. The lower electrode, the oxide layer and the upper electrode constitute a capacitor on the field oxide layer.
A drawback in the conventional method described above is that a portion of the second polysilicon layer as a spacer remains on the sidewall of the lower electrode of the capacitor. The remaining second polysilicon layer is called a "stringer". Since the material of the stringer is a conductor, an unexpected electric conduction is formed to cause shorts between the capacitor and other devices on the substrate.
Another drawback in the conventional method described above is that an additional step, such as an isotropic etching, is required to remove the stringer. The isotropic etching not only removes the stringer but also etches the gate oxide layer. The gate oxide layer may be removed to expose the substrate because a thickness of the gate oxide layer is only about 50-100 .ANG.. Removing the gate oxide layer results in transistor failure.
Yet another drawback in the conventional method is that when performing the step of isotropic etching to remove the stringer, a part of the side-wall of the upper electrode and the oxide layer (inter-poly dielectric layer) between the upper electrode and the lower electrode are etched. Furthermore, the capacitance of the capacitor is controlled by a thickness of the inter-poly dielectric layer. Because the inter-poly dielectric layer is etched during performing the isotropic etching, the quality of the capacitor cannot be controlled because the thickness of the inter-poly dielectric layer is difficult to controlled.
FIGS. 1A to 1E are schematic, cross-sectional views showing a conventional process for forming a mixed mode device. In FIG. 1A, a field oxide layer 102 is formed on a provided substrate 100 to isolate active regions (not shown) on the substrate 100. A pad oxide layer 104 is formed on the active regions. A first polysilicon layer 106 is formed on the pad oxide layer 104 and on the field oxide layer 102 by chemical vapor deposition (CVD).
In FIG. 1B, a part of the first polysilicon layer 106 is removed to form a lower electrode 106a of a capacitor on the field oxide layer 102, using a photoresist layer (not shown).
In FIG. 1C, the pad oxide layer 104 is removed. A gate oxide layer 108 is formed on the active regions by thermal oxidation. An oxide layer 110 is formed on the surface of the lower electrode 106a when forming the gate oxide layer 108. A conformal second polysilicon layer 112 is formed over the substrate 100 by CVD.
In FIG. 1D, a silicide layer 114 is formed on the second polysilicon layer 112.
In FIG. 1E, according to a defined pattern of a photoresist layer, a part of the silicide layer 114 and a part of the second polysilicon layer 112 are removed to form an upper electrode of the capacitor and to form a gate of a transistor by anisotropic etching. The capacitor and the transistor constitute a mixed mode devices. The upper electrode consists of the second polysilicon layer 112a and silicide layer 114a. The gate consists of the second polysilicon layer 112b and silicide layer 114b.
However, a portion of the second polysilicon layer 112 remains to form a stringer 112c on the sidewall of the lower electrode during anisotropic etching. Since the stringer 112c is a conductor, the stringer 112 may conduct electrically with other devices to make the devices short. An isotropic etching step is performed to removed the stringer 112c but the lower electrode 112a and the second polysilicon layer 112b of the gate are etched at the same time. The isotropic etching step even etches the oxide layer 110 as a dielectric layer of the capacitor and the gate oxide layer 108 to destroy the transistor and to affect the quality of the capacitor.